LT1939
20
1939f
APPLICATIONS INFORMATION
increases the overall ef ciency of the system. However,
the minimum V
IN
increases to 2V plus the V
GS
at full load
of the transistor. Additionally, due to a lack of beta current
limiting, a shorted output can cause the switcher output
of the LT1939 to collapse.
Since the collector of the LDRV npn is connected internally
to V
IN
, you must consider the impact of LDRV current on
ef ciency and die temperature when con guring the linear
regulator/controller. For example, with V
IN
= 25V, LDRV =
3.3V and I
LDRV
= 10mA, power dissipation on the die will
be 217mW. For a typical 3.3V/1A switcher application,
this represents an additional 7% ef ciency loss and ap-
proximately 10 degrees rise in die temperature.
If the linear output of the LT1939 is not used, the LDRV
pin should be shorted to the LFB Pin.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 11
shows the high di/dt paths in the buck regulator circuit.
Note that large switched currents ow in the power switch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board and their connections should be made on that layer.
Place a local, unbroken ground plane below these com-
ponents, and tie this ground plane to system ground at
Figure 9. Linear Regulator Transient Response
Figure 10. Linear Controller
To compensate the linear regulator, simply add a ceramic
capacitor from the LDRV pin to ground. Typical values
range from 0.01糉 to 1糉. Figure 9 illustrates the transient
response with a 0.47糉 output capacitor.
Linear Controller
By adding an external follower (NPN or NMOS), the LFB
and LDRV pins can be con gured as a controller (Fig-
ure 10) for a low dropout regulator with increased output
capability.
The output current capability of Figure 10s circuit is a
product of the LDRV current limit and beta of the external
NPN which is normally less than the current capability of
the LT1939. The dropout voltage for the circuit is set by the
saturation voltage of the external NPN, which is typically
300mV. The minimum V
IN
for the circuit to function prop-
erly is 2V plus the base emitter drop of the external NPN.
Replacing the NPN in Figure 10 with a NMOS transistor
can reduce the dropout voltage down to the R
DS(ON)
of the
NMOS times the output current of the regulator. This also
20約/DIV
1939 F09
V
OUT
AC COUPLED
20mV/DIV
LOAD STEP
2.5mA TO 7.5mA
5mA/DIV
L1
3.3糎
C5
0.47糉
C7
22糉
C6
22糉
R1
27.4k
R2
8.06k
C1
2.2糉
C2
0.47糉
4.5V TO 25V
R6
40.2k
R5
49.9k
C3
220pF
1939 F10
V
OUT1
3.5V
V
OUT2
3.3V
1A
D2
BAT54
D1
B240A
BST
V
IN
SW
FB
SHDN
SS
LT1939
R
T/
SYNC
V
C
LDRV
PG
LFB
PG
R4
8.06k
R3
24.9k
Q1
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